The circuits using a programmable array have been developed as ASIC (application specified ICs), that is, as small-quantity products or trial products. Conventionally, the typical circuits using the programmable array are GAs (gate arrays) and SCs (standard cells) customized from the mask level so as to satisfy the specifications required by the user, or PLAs (programmable logic arrays) customized by the user itself. In the case of the SCs, logic circuit blocks used in an LSI(Large Scale Integration) are previously registered in a computer, and products required by the user are designed by arranging and connecting these logic circuit blocks through the automatic processing by use of the computer. Further, in the case of the GAs, basic circuits for constituting logic gates are previously formed into an array pattern on a semiconductor substrate, and the user manufactures any desired LSI by deciding the wiring pattern using an automatic wiring software in the same way as with the case of the standard cells. The above-mentioned methods have such advantages that the period required for development is relatively short, as compared with the ordinary LSI which is totally designed from the beginning. In these methods, however, there still exists a problem in that it takes several weeks or several months from the design end to the production completion, because the manufacturing process is still required after the user has finished the design by the automatic wiring software. In other words, in the case of the GAs and SCs, although there exists such an advantage that any required circuits can be realized, a long development period is needed and thereby the development cost is relatively higher than that of the PLAs. In contrast with this, in the case of the PLAs, although the cost is low and the development period is short, there exists a limit in the actually realizable circuits.
To overcome the shortcomings involved in both the circuit devices, recently, a circuit device referred to as FPGA (field programmable gate array) has been developed, by which any given circuits (as with the case of the GAs) can be developed by the user (as with the case of the PLAs). In this FPGA, there are previously arranged basic cells (each composed of a single of or a plurality of transistors), interconnections for connecting these basic cells, and programmable elements, so that any desired circuits can be obtained by the user by programming these programmable elements. As this circuit device, various devices provided with different programmable elements and different basic cells are now being developed.
FIGS. 26 and 27 show examples of the FPGA cells so far known. In the case of the device shown in FIG. 26, programmable elements 102a and 102b are arranged around a multiplexer 101, and any logic with respect to any number of input signals (e.g., three input signals in FIG. 26) can be stored as a table. In this FPGA cell, any required circuit can be realized as follows: in order to store a logic according to the three input signals IN1, IN2 and IN3 in the multiplexer 101 as a table, the data input terminals of the multiplexer 101 are so designed as to be fixed to a VDD level or a GND level by use of the programmable elements 102a and 102b. Therefore, when the user programs these programmable elements, it is possible to store the outputs of any desired logic according to all the input patterns of the input signals. Consequently, when the input signal lines IN1, IN2 and IN3 are connected to the control input terminals of the multiplexer 101, the multiplexer 101 can output the output signals on the output terminal OUT in accordance with the input signals applied thereto and the logic table stored therein.
In the case of the device shown in FIG. 27, programmable elements 102a and 102b are arranged at the respective nodes of unit transistors 104 and 105. Therefore, by programming the programmable elements 102a and 102b, it is possible to construct a desired circuit by the unit transistors, as with the case of the GA.
In the case where the multiplexer is used, although there exists such an advantage that any given logic circuits can be realized, there exists such a drawback that the efficiency of cell utilization is reduced according to the logic circuits required to be realized. On the other hand, in the case of the unit transistors, although the efficiency of the cell utilization is high, there exist such problems in that: since a floating capacitance is added to the node of each of the transistors, the operating speed decreases; and further since the number of the programmable elements increases, a stand-by current of the device increases due to leak current of the programmable elements.
Further, the FPGA is one of the semiconductor integrated circuits, in which the interconnections between plural cells can be designed by the user. Therefore, it is desirable to prepare a necessary number of interconnections of a required length so that the user can design a desired circuit. In the conventional integrated circuits, however, there exists no definite rule with respect to the interconnection length distribution on which the interconnecting resources are to be decided. Consequently, in FPGAs whenever the user designs the interconnections in practice, there exists a problem in that the inerconnection length is excessive and thereby some regions of the basic circuits are wasteful or conversely the interconnection length is not sufficient.
In summary, the conventional FPGA involves such drawbacks that the efficiency of cell utilization is low; the operating speed is low; the stand-by current is high, etc. In addition, in the integrated circuits whose interconnection can be designed by the user, the interconnecting resources are excessively long and wasteful or insufficiently short, with the result that the effective utilization of the chip area cannot be realized.